ausgewählte Veröffentlichungen

• Artikel

  • Improvement of low-frequency noise behavior with chloridic precursor materials at ALD process.  Memories - Materials, Devices, Circuits and Systems, p. 100095.  2023
  • Germanium Nanowire Reconfigurable Transistor Model for Predictive Technology Evaluation.  IEEE transactions on nanotechnology, Vol.21, pp. 728-736.  2022
  • Vertically Integrated Reconfigurable Nanowire Arrays.  IEEE electron device letters, Vol.39(8), pp. 1242-1245.  2018
  • Enabling Energy Efficiency and Polarity-Control in Germanium Nanowire Transistors by Individually Gated Nano-Junctions 2017
  • Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents.  IEEE transactions on nanotechnology, Vol.16(5), pp. 812-819.  2017
  • The RFET-a reconfigurable nanowire transistor and its application to novel electronic circuits and systems 2017
  • Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors.  Solid-state electronics, Vol.128, pp. 148-154.  2017
  • (Invited) High-Yield Reconfigurable Silicon and Germanium Nanowire Transistors and Compact Logic Circuits.  Meeting abstracts (Electrochemical Society), Vol.MA2016-02(37), pp. 2315-2315.  2016
  • Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors.  IEEE transactions on nanotechnology, Vol.14(4), pp. 689-698.  2015
  • Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors.  IEEE electron device letters, Vol.36(10), pp. 991-993.  2015
  • Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized? 2010

• Dokument

  • Entwicklung von energieeffizienten Hochleistungstransistoren.  WissenD das Magazin der Hochschule für Technik und Wirtschaft Dresden , Vol.20(2), pp. 20-23. 2012

• Tagungsband

  • Scaling Aspects of Nanowire Schottky Junction based Reconfigurable Field Effect Transistors.  2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), pp. 1-4. 2019
  • A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.  2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Vol.2018-, pp. 605-608. 2018
  • Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits.  2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 169-174. 2016
  • Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors.  2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), pp. 1-4. 2016
  • Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits.  EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, pp. 17-20. 2015
  • Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond.  2012 International Semiconductor Conference Dresden-Grenoble (ISCDG), pp. 61-63. 2012
  • Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process.  2011 International Semiconductor Device Research Symposium (ISDRS), pp. 1-2. 2011