Effect of independently sized gates on the delay of reconfigurable silicon nanowire transistor based circuits

Reconfigurable silicon nanowire field effect transistors (RFETs) provide both operation modes of p-type and n-type field effect transistors in a single multigate device. This unique feature provides additional degrees of freedom in terms of circuit design and device layout. Here a device-circuit co-design study of a novel 1-bit full adder with only 20 transistors is presented. The delay of the adder is analyzed using the logical effort theory and compared to standard CMOS implementation. The effect of independent gate sizing on device and circuit characteristics will be discussed. It will be shown that asymmetric gates can be exploited to reduce the critical delay of the new adder by 15 %, although the individual device performance is kept constant.

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