Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process

For future scaling to the end of the ITRS roadmap, novel structures like FinFETs are required to improve electrostatic integrity of MOSFETs with gate lengths shorter than 35 nm [1-4]. Classic fully-depleted FinFETs with a high aspect ratio are not compatible with existing planar process flows. A Tri-Gate transistor has the advantage of being more compatible. It is even possible to produce low-profile Tri-Gates in parallel to planar MOSFETs [5], with shared Tri-Gate and planar implants and common-use of source/drain epi and dual band-edge metal gate workfunctions. This maintains the design flow, saves mask count, allows reuse of analog and high-voltage I/O designs, while exploiting Tri-Gates in high speed logic and low minimum voltage.

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