Strain-engineering for improved tunneling in reconfigurable silicon nanowire transistors

Mechanical stress has the potential to be an efficient performance booster for diverse emerging research devices based on tunneling phenomena, such as tunnel FETs, resonant tunnel FETs and reconfigurable FETs. The effect is highly dependent on the constellation between the stress source and the crystal orientation. Although stress engineering is well established for enhancement carrier mobility, it is rather unexplored for the control of tunneling. In this work stress profiles formed by four different sources are studied by device simulations of reconfigurable silicon nanowire transistor using two independently gated Schottky junctions. Self-limited oxidation of the intrinsic silicon nanowire is used as an example to describe the effects of mechanical stress on the multi-valley band structure applying the deformation potential theory and on the average effective tunneling mass. The transfer characteristics of strained n- and p-type transistors are analyzed with respect to the current ratio between electron and hole conduction which is important to implement reconfigurable CMOS circuits. It has been verified that mechanical stress formed by oxidation as well as stressed top layers are effective options to control the current injection through the Schottky junctions and thus to achieve symmetric operation of reconfigurable nanowire devices.

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