ausgewählte Veröffentlichungen

• Abschnitt eines Buches

  • Bauelementesimulation zum Entwurf eines vertikalen GaN-MOSFET mit einer Durchbruchspannung von 1 kV

• Artikel

  • Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized? 2010
  • Detailed simulation study of embedded SiGe and Si:C S/D stressors in nano scaled SOI MOSFETs 2010
  • Effect of source/drain extension dopant species on device performance of non-diffuse embedded SiGe strained SOI P-MOSFETs. 2010
  • Simulation of asymmetric doped high performance SOI MOSFETs for VLSI CMOS technologies 2010
  • Understanding strain-induced drive-current enhancement in strained-silicon n-MOSFET and p-MOSFET. 2010

• Dokument

  • Entwicklung von energieeffizienten Hochleistungstransistoren.  WissenD das Magazin der Hochschule für Technik und Wirtschaft Dresden , Vol.20(2), pp. 20-23. 2012

• Konferenz-Poster

  • Investigation of advanced FDSOI CMOS devices for analog/mixed signal applications 2019

• Tagungsband

  • Message from Conference Chairs.  The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, pp. viii-viii. 2021
  • Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond.  2012 International Semiconductor Conference Dresden-Grenoble (ISCDG), pp. 61-63. 2012
  • Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process.  2011 International Semiconductor Device Research Symposium (ISDRS), pp. 1-2. 2011