ausgewählte Veröffentlichungen
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Konferenz-Paper
- Mobility and strain effects for <100> and <110> oriented silicon and SiGe transistor channels 2012
- Suppression of the corner effects in a 22 nm hybrid tri-gate/planar process 2011
- Optimization of Stressor Overlayer Parameters for MOSFET's in "Cool Silicon" – Technologies 2010
- Analyse und Optimierung von verspannten Schichten auf CMOS–Transistoren
- Simulation and Optimization of Tri-Gates in a 22nm Hybrid Tri-Gate/Planar Process
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Wissenschaftlicher Artikel
- Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model. Mathematics (Basel), Vol.5(4), p. 68. 2017
- Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized? 2010
- Detailed simulation study of embedded SiGe and Si:C S/D stressors in nano scaled SOI MOSFETs 2010
- Effect of source/drain extension dopant species on device performance of non-diffuse embedded SiGe strained SOI P-MOSFETs. 2010
- Simulation of asymmetric doped high performance SOI MOSFETs for VLSI CMOS technologies 2010
- Understanding strain-induced drive-current enhancement in strained-silicon n-MOSFET and p-MOSFET. 2010