ausgewählte Veröffentlichungen

• Abschnitt eines Buches

  • Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level 2000
  • Formal Verification of a Reconfigurable Microprocessor 2000
  • Hazard checking in pipelined processor designs using symbolic model checking 1999

• Artikel

  • Automated Formal Verification of Routing in Material Handling Systems.  IEEE transactions on automation science and engineering, Vol.10(4), pp. 900-915.  2013
  • Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking.  Theoretical computer science, Vol.404(3), pp. 293-307. 

• Dokument

  • On the formal verification of routing in material handling systems.  2012 IEEE International Conference on Automation Science and Engineering (CASE), pp. 8-13. 2012